Zak Smith's Resume real-life
topic: Not currently looking
Objective: To contribute to the design of leading-edge digital systems, within a team of highly-motivated engineers enabled to succeed by management.
Specific Interests: Computer architecture, logic design, verification, software engineering, VLSI.
formats: HTML (11.3kB) 2001-07-11 quality 5
Back to list of documents

Zak Smith

U.S. Citizen
Fort Collins, Colorado
To use versatile problem-solving skills to make a difference.
Quick-learning, versatile, excellent problem solving skills, strategic planning, architected solutions, problem identification, organizational dynamics, detail oriented, excellence as habit.
Specific Interests
Weapons Systems,
Highly Educated
MS Electrical Engineering, University of Wisconsin - Madison, 1998 4.0 GPA
BS Electrical Engineering, Second major Computer Science, University of Wisconsin - Madison, 1997 3.8 GPA
Experience doing basic research
Extra-professional experience
Skill-at-arms: "Practical" pistol, rifle, and shotgun shooter: 3Gun, USPSA
Founding Member: Colorado Multigun
Author articles papers on long range rifle optics and ballistics
Inventor of 23 patents filed to the US Patent Office.
Co-author of two published papers.

Professional Experience
Intel Corp, Enterprise Processor Division, Fort Collins, CO, 2/2005 - present

Next-generation IA-64 (IPF) CPU functional verification

  • Core / Link verification methodology and tool development
  • Random code/test tool development

Hewlett-Packard, Systems VLSI Technology Division, Fort Collins, CO. 2/1999 - 1/2005

Montecito IA-64 (IPF) CPU functional verification:

  • Control and Verification Errors "czar", responsible for making sure error strategy is
    • complete: that it is fully defined, meets value-chain requirements, and is fully implemented,
    • coherent: that it consistent and works properly with the architecture, and
    • correct: that the implementation is correct and has been appropriately verified
    Fulfillment of this task requires coordinating with RTL authors, coverage czar, focus test-case writers, RCG authors and pilots and delegating responsibility.
  • Lockstep mode verification "czar", similar to Error czar role described above
    • methodology,
    • implementation and maintenance of checkers,
    • turn-on of mode,
    • focus verification,
    • definition of rest of tool-chain
  • Legacy ISA Emulator verification "czar", responsible for making sure the emulator logic is complete, coherent, and correct. The scope of this role is similar to the Error czar role described above.
  • Cross-functional verification go-to guy. Volunteered to work on "in trouble" area of design, utilizing a variety of cross-functional methods and tools to solve the problem, on time.
  • Scoped-out and developed a chip interface translator enabling leverage of old tool-chain with new chip link. Saved approx 6 months.

McKinley CPU functional verification:

  • IA-64 (IPF) architecture and assembly,
  • IA-32 (x86) architecture and assembly,
  • random-code verification tools,
  • pre-silicon verification of architectural, micro-architectural, and HDL models,
  • post-silicon verification and debug of prototype systems,
  • management and regression of large "legacy" test suite,
  • infrastructure automation and reliability,
  • version control and release methodologies,
  • porting code between HPUX (PA), Linux (x86 and IA64), and corresponding C/C++ compilers,
  • expert in writing endian-neutral code and endian-sanitizing old code,
  • web-based, database-backed, team collaboration and individual productivity tools.
  • Large and small C++ & C applications,
  • Perl scripts of all sizes,
  • Shell scripting, UNIX automation,
  • Postgres/SQL, PHP 3.0+, HTML,
  • HPUX & Linux setup and sysadmin.

Hewlett-Packard, Systems VLSI Technology Operation, Fort Collins, CO. Summer 1998

McKinley CPU fuse block:

Hewlett-Packard, Systems Technology Division, Cupertino, CA. Summer 1997

SuperDome chipset 72-bit ECC block:

  • logic design,
  • verification using C, Perl, and HDL models,
  • circuit design,
  • VLSI design using standard cells.

Hewlett-Packard, Logic Analyzer Division, Colorado Springs, CO. Summer 1996

As an intern, I ported an X-Window call-tracking database to HP-PA workstations, in addition to developing a method to automatically update firmware on logic emulation devices via standard network protocols. Tools: Tcl/Tk, UNIX shell.

Computer-Aided Engineering, Univ. of Wisconsin - Madison, 8/1994 - 12/1998

As a member of the Unix system administration and systems programming staff, I developed and maintained custom tools for network management and did all the normal Unix admin stuff for several hundred workstations and a room full of servers. Specialties: HP-UX, Linux, networks, security, RSA-type public/private key encryption.

UW-Madison, ECE554, Fall 1996

I led a 5 person team that developed a superscalar computer from instruction set specification to hardware and software debug. The design was implemented in 6 Xilinx XC4000 FPGAs. Tools: Mentor Graphics, Xilinx tools, UNIX shell.

ECE Department, Microwave Lab, UW-Madison, 1/1995 - 6/1995

As a lab assistant for Prof. John Booske, I developed some data-acquisition software that drove a LeCroy oscilloscope from a PC via GPIB (IEEE488.2). I also set up particle-in-cell (PIC) simulations for electron beams in microwave generators, and wrote code to process the output. Tools: C, Perl, MAGIC PIC.

Self-Employed Programmer & Consultant, 1991 - 1993

While I was in high-school, I operated a dial-in computer bulletin board system, using the "Searchlight BBS." I wrote some software to enhance operation of my own system, and based on feedback and demand from other operators, I developed, marketed, sold, and supported several software products. Tools: Turbo-Pascal (OOP).


  • Primary inventor of 15 filed patents related to CPU verification.
  • Co-inventor of 8 filed patents related to CPU verification


Smith, Zak: "The 6.8 SPC, Is it all that?". Shotgun News 60(21):4-16. July 31, 2006.

The Use Of A Fully Connected Neural Network For Signal Interrelationship Rule Derivation In An Architectural Model, John Maly, Ryan Thompson, Zachary Smith, Research Disclosure, March 2004.

Improving Branch Predictors by Correlating on Data Values, Timothy H. Heil, Zak Smith, J.E. Smith, Proceedings of the 32nd Annual International Symposium on Microarchitecture, Nov 1999.


MSEE, University of Wisconsin - Madison, 12/1998. GPA 4.0
Research: Using Data Values to Aid Branch Prediction, Advisor Prof. James E. Smith
Computer architecture & micro-architecture, VLSI, Fault-tolerance, Real-time computing, Testing & testability.

BSEE, University of Wisconsin - Madison, 5/1997. GPA 3.834
Electrical & Computer Engineering. Second major Computer Science.

University of Wisconsin - Milwaukee & Carroll College - Waukesha, WI
Took 11 computer science credits while high-school student.

Projects and papers of note:


Preferred: Perl, C, C++, UNIX shell, emacs, HP-UX, Linux, AFS, HTML, PHP.
Some Exposure: Pascal, LISP, Tcl/Tk, LaTeX, Verilog, Solaris

Honors & Awards

  • Recipient of Graduate School Fellowship, 9/1997
  • Rohn Scholarship, 9/1996
  • Fred W. and Josephine H. Colbeck Scholarship, 5/1995
  • G. P. Ryan and W. G. Kirchoffer Engineering Freshman Merit Award
  • The College Board's A. P. Scholar with Distinction Award
  • Navy Distinguished Achievement Award - Marquette Science Fair
  • Member: Eta Kappa Nu, Tau Beta Pi, Phi Kappa Phi, IEEE, National Honor Society, Golden Key

[Zak Smith] [] [/~zak/documents/real-life/zaks-resume/html]
$Id: documents,v 1.5 2000/09/28 21:20:39 zak Exp zak $
documents was last modified Mon 07 Apr 2014 0:16:32
All text and photographs © copyright 1997-2009 Zak Smith, all rights reserved, unless otherwise noted.
documents took 1.65 msec and 1 queries to generate, at Mon 23 Sep 2019 6:12:22.