| RRisc Architecture Report |
college |
| topic: |
ECE554 (Digital Engineering Laboratory) |
|
The mission of UW--Madison's ECE 554 students is to Design a
non--trivial computer with an original instruction set. This document
describes the superscalar architecture developed by the RRisc team and
how it was implemented in Xilinx XC4000 FPGAs using the WICEPS
prototype board.
|
| formats: |
Adobe PDF (397.7kB), PostScript (301.3kB), TeX (2.3kB)
|
1996-12-17 |
quality 5 |
|
\documentclass{report}
\begin{document}
\newcommand{\pname}{$\mathcal{R} \mathcal{R} \mathcal{I} \mathcal{S} \mathcal{C}$\ }
\newcommand{\I}[1]{{\tt {#1}}}
\newcommand{\NOP}{\I{NOP}}
\newcommand{\AND}{\I{AND}}
\newcommand{\OR}{\I{OR}}
\newcommand{\SLL}{\I{SLL}}
\newcommand{\hex}[1]{{\tt 0x#1}}
\newcommand{\R}[1]{{\tt \$#1}}
\newcommand{\sig}[1]{{\sl #1}}
%\newcommand{\PC}{\textsf{PC}}
%\newcommand{\AR}{\textsf{AR}}
%\newcommand{\SP}{\textsf{SP}}
%\newcommand{\SET}{\textsf{SET}}
%\newcommand{\CY}{\textsf{CY}}
\newcommand{\PC}{{\tt PC}}
\newcommand{\AR}{{\tt AR}}
\newcommand{\SP}{{\tt SP}}
\newcommand{\SET}{{\tt SET}}
\newcommand{\CY}{{\tt CY}}
\begin{titlepage}
\title{\pname Architecture Report
\thanks{We would like to thank the TAs Gebre Gessesse and
Zhenyu (Jerry) Liu and Professor Kime for their help during
the course of the semester.}
\thanks{This is the condensed version of the report and
as such does not contain the schematics or figures.}
}
\author{
Zak Smith \and
Jeffry Lucman \and
Jeremy Petsinger \and
John Liu \and
Mostafa Arifin
}
\maketitle
\begin{abstract}
The mission of UW--Madison's ECE 554 students is to {\it Design a
non--trivial computer with an original instruction set.} This document
describes the superscalar architecture developed by the \pname team and
how it was implemented in Xilinx XC4000 FPGAs using the WICEPS
prototype board.
\end{abstract}
\end{titlepage}
\newpage
\tableofcontents
\newpage
\chapter{Instruction Set Architecture}
\include{poo}
\chapter{Machine Architecture}
\include{march}
\chapter{Memory Subsystem}
\include{memi}
\chapter{Dispatch Subsystem Design}
\include{dsp}
\chapter{Master \& Slave ALU Pipe Design}
\include{aio}
\chapter{Memory Pipe Design}
\include{mem}
\chapter{Register File Design}
\include{reg}
\chapter{Superscalar Performance}
\include{super}
\chapter{Macro Assembler}
\include{mad}
\chapter{Individual Contributions}
\include{contrib}
\chapter{Limits and Epilogue}
\include{limits}
\chapter{DELA Definition}
\include{dela}
\chapter{Software}
(not included due to space considerations)
\chapter{Annotated Quicksim Traces}
(not included due to space considerations)
\chapter{Full Schematics}
(not included due to space considerations)
\end{document}
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